//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2012-2013 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 149905
// File Date           :  2013-05-08 18:27:40 +0100 (Wed, 08 May 2013)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Verilog-2001 (IEEE Std 1364-2001)
//------------------------------------------------------------------------------
// Purpose : HDL design file for AMBA master interface block
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//                               nic400_amib_tpv_gp_apb4_ysyx_rv32.v
//                               =============
//
//------------------------------------------------------------------------------
//
//  Overview
// ==========
//
//   The Axi Master Interface Block provides an interface between an interconnect
// and an external slave port on NIC400.
//
//   The AMIB can be configured to provide four modes of operation for each of
// the channels:
//    1. fully registered (total timing isolation between
//                         master and slave ports)
//    2. forward path registered only (timing isolation on data/ctrl/valid
//                                     paths only)
//    3. reverse path registered only (timing isolation on ready paths only)
//
//------------------------------------------------------------------------------


`include "nic400_amib_tpv_gp_apb4_defs_ysyx_rv32.v"

module nic400_amib_tpv_gp_apb4_ysyx_rv32
  (
  
    //APB Bus
    paddr_uart_slv_apb4_tpv,
    pwdata_uart_slv_apb4_tpv,
    pwrite_uart_slv_apb4_tpv,
    pprot_uart_slv_apb4_tpv,
    pstrb_uart_slv_apb4_tpv,
    penable_uart_slv_apb4_tpv,
    psel_uart_slv_apb4_tpv,
    prdata_uart_slv_apb4_tpv,
    pslverr_uart_slv_apb4_tpv,
    pready_uart_slv_apb4_tpv,

    //APB Bus
    paddr_spfs_slv_apb4_tpv,
    pwdata_spfs_slv_apb4_tpv,
    pwrite_spfs_slv_apb4_tpv,
    pprot_spfs_slv_apb4_tpv,
    pstrb_spfs_slv_apb4_tpv,
    penable_spfs_slv_apb4_tpv,
    psel_spfs_slv_apb4_tpv,
    prdata_spfs_slv_apb4_tpv,
    pslverr_spfs_slv_apb4_tpv,
    pready_spfs_slv_apb4_tpv,

    //APB Bus
    paddr_i2s_slv_apb4,
    pwdata_i2s_slv_apb4,
    pwrite_i2s_slv_apb4,
    pprot_i2s_slv_apb4,
    pstrb_i2s_slv_apb4,
    penable_i2s_slv_apb4,
    psel_i2s_slv_apb4,
    prdata_i2s_slv_apb4,
    pslverr_i2s_slv_apb4,
    pready_i2s_slv_apb4,

    //slave_11_s ITB bus

    //A Channel
    aid_slave_11_s,
    aaddr_slave_11_s,
    alen_slave_11_s,
    asize_slave_11_s,
    aburst_slave_11_s,
    alock_slave_11_s,
    acache_slave_11_s,
    aprot_slave_11_s,
    awrite_slave_11_s,
    avalid_slave_11_s,
    aregion_slave_11_s,
    aready_slave_11_s,

    //W Channel
    wdata_slave_11_s,
    wstrb_slave_11_s,
    wlast_slave_11_s,
    wvalid_slave_11_s,
    wready_slave_11_s,

    //D Channel
    did_slave_11_s,
    ddata_slave_11_s,
    dresp_slave_11_s,
    dlast_slave_11_s,
    dbnr_slave_11_s,
    dvalid_slave_11_s,
    dready_slave_11_s,

    //Clock and reset signals
    apb_pclken,
    aclk,
    aresetn

  );




  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------
  
  //APB Bus
  output  [31:0]      paddr_uart_slv_apb4_tpv;  
  output  [31:0]      pwdata_uart_slv_apb4_tpv; 
  output              pwrite_uart_slv_apb4_tpv; 
  output  [2:0]       pprot_uart_slv_apb4_tpv;  
  output  [3:0]       pstrb_uart_slv_apb4_tpv;  
  output              penable_uart_slv_apb4_tpv;
  output              psel_uart_slv_apb4_tpv;   
  input   [31:0]      prdata_uart_slv_apb4_tpv; 
  input               pslverr_uart_slv_apb4_tpv;
  input               pready_uart_slv_apb4_tpv; 

  //APB Bus
  output  [31:0]      paddr_spfs_slv_apb4_tpv;  
  output  [31:0]      pwdata_spfs_slv_apb4_tpv; 
  output              pwrite_spfs_slv_apb4_tpv; 
  output  [2:0]       pprot_spfs_slv_apb4_tpv;  
  output  [3:0]       pstrb_spfs_slv_apb4_tpv;  
  output              penable_spfs_slv_apb4_tpv;
  output              psel_spfs_slv_apb4_tpv;   
  input   [31:0]      prdata_spfs_slv_apb4_tpv; 
  input               pslverr_spfs_slv_apb4_tpv;
  input               pready_spfs_slv_apb4_tpv; 

  //APB Bus
  output  [31:0]      paddr_i2s_slv_apb4;       
  output  [31:0]      pwdata_i2s_slv_apb4;      
  output              pwrite_i2s_slv_apb4;      
  output  [2:0]       pprot_i2s_slv_apb4;       
  output  [3:0]       pstrb_i2s_slv_apb4;       
  output              penable_i2s_slv_apb4;     
  output              psel_i2s_slv_apb4;        
  input   [31:0]      prdata_i2s_slv_apb4;      
  input               pslverr_i2s_slv_apb4;     
  input               pready_i2s_slv_apb4;      

  //slave_11_s ITB bus


  //A Channel
  input   [3:0]       aid_slave_11_s;                 //id of slave_11_s bus
  input   [31:0]      aaddr_slave_11_s;               //address of slave_11_s bus
  input   [7:0]       alen_slave_11_s;                //length field of slave_11_s bus
  input   [2:0]       asize_slave_11_s;               //size of slave_11_s bus
  input   [1:0]       aburst_slave_11_s;              //burst length of slave_11_s bus
  input               alock_slave_11_s;               //lock of slave_11_s bus
  input   [3:0]       acache_slave_11_s;              //cache field of slave_11_s bus
  input   [2:0]       aprot_slave_11_s;               //prot field of slave_11_s bus
  input               awrite_slave_11_s;              //direction of slave_11_s bus
  input               avalid_slave_11_s;              //valid of slave_11_s bus
  input   [3:0]       aregion_slave_11_s;             //region selection signal of slave_11_s bus
  output              aready_slave_11_s;              //ready of slave_11_s bus

  //W Channel
  input   [31:0]      wdata_slave_11_s;               //write data of slave_11_s AXI bus W Channel
  input   [3:0]       wstrb_slave_11_s;               //write strobes of slave_11_s AXI bus W Channel
  input               wlast_slave_11_s;               //write last of slave_11_s AXI bus W Channel
  input               wvalid_slave_11_s;              //write valid of slave_11_s AXI bus W Channel
  output              wready_slave_11_s;              //write ready of slave_11_s AXI bus W Channel

  //D Channel
  output  [3:0]       did_slave_11_s;                 //id of slave_11_s bus
  output  [31:0]      ddata_slave_11_s;               //data of slave_11_s bus
  output  [1:0]       dresp_slave_11_s;               //response status of slave_11_s bus
  output              dlast_slave_11_s;               //last of slave_11_s bus
  output              dbnr_slave_11_s;                //response type of slave_11_s bus
  output              dvalid_slave_11_s;              //valid of slave_11_s bus
  input               dready_slave_11_s;              //ready of slave_11_s bus

  //Clock and reset signals
  input               apb_pclken;                     //apb master port clock enable
  input               aclk;                           //main clock
  input               aresetn;                        //main reset



  //----------------------------------------------------------------------------
  // Internal wires
  //----------------------------------------------------------------------------



  wire           w_master_port_dst_valid;
  wire           w_master_port_dst_ready;
  wire           w_master_port_src_valid;
  wire           w_master_port_src_ready;

  wire [36:0]    w_master_port_src_data;     // concatenation of the inputs
  wire [36:0]    w_master_port_dst_data;     // concatenation of the registered inputs


  // W Channel
  wire [31:0]    wdata_apb;
  wire [3:0]     wstrb_apb;
  wire           wlast_apb;
  wire           wvalid_apb;
  wire           wready_apb;



  //----------------------------------------------------------------------------
  // Internal APB wires
  //----------------------------------------------------------------------------
  wire                            penable_apb;          // Common APB PENABLE
  wire                            pwrite_apb;           // Common APB PWRITE
  wire [31:0]                     paddr_apb;            // Common APB PADDR
  wire [31:0]                     pwdata_apb;           // Common APB PWDATA

  wire [2:0]                      pprot_apb;            // Common APB PPROT
  wire [3:0]                      pstrb_apb;            // Common APB PSTRB

  // ---------------------------------------------------------------------------


  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------


  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at Master Port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign w_master_port_src_data = {wdata_slave_11_s,
        wstrb_slave_11_s,
        wlast_slave_11_s};

  // expand the concatenated registered values to the master port outputs
  assign {wdata_apb,
        wstrb_apb,
        wlast_apb} = w_master_port_dst_data;

  assign wvalid_apb = w_master_port_dst_valid;
  assign w_master_port_dst_ready = wready_apb;

  assign w_master_port_src_valid = wvalid_slave_11_s;
  assign wready_slave_11_s = w_master_port_src_ready;


  //----------------------------------------------------------------------------
  // APB Protocol conversion
  //----------------------------------------------------------------------------
  nic400_amib_tpv_gp_apb4_apb_m_ysyx_rv32 #(
    .ID_WIDTH         (4),
    .ADDR_WIDTH       (32)
  ) u_apb_m
  (
    .aclk             (aclk),
    .aresetn          (aresetn),

    .awrite           (awrite_slave_11_s),
    .aid              (aid_slave_11_s),
    .aaddr            (aaddr_slave_11_s),
    .alen             (alen_slave_11_s),
    .asize            (asize_slave_11_s),
    .aburst           (aburst_slave_11_s),
    .aregion          (aregion_slave_11_s),
    .aprot            (aprot_slave_11_s),

    .avalid           (avalid_slave_11_s),
    .aready           (aready_slave_11_s),

    .dbnr             (dbnr_slave_11_s),
    .did              (did_slave_11_s),
    .ddata            (ddata_slave_11_s),
    .dresp            (dresp_slave_11_s),
    .dlast            (dlast_slave_11_s),
    .dvalid           (dvalid_slave_11_s),
    .dready           (dready_slave_11_s),

    .wdata            (wdata_apb),
    .wstrb            (wstrb_apb),
    .wlast            (wlast_apb),
    .wvalid           (wvalid_apb),
    .wready           (wready_apb),

    .pclken           (apb_pclken),
    .psel_uart_slv_apb4_tpv_i     (psel_uart_slv_apb4_tpv),
    .psel_spfs_slv_apb4_tpv_i     (psel_spfs_slv_apb4_tpv),
    .psel_i2s_slv_apb4_i     (psel_i2s_slv_apb4),
    .pready_uart_slv_apb4_tpv_i   (pready_uart_slv_apb4_tpv),
    .pready_spfs_slv_apb4_tpv_i   (pready_spfs_slv_apb4_tpv),
    .pready_i2s_slv_apb4_i   (pready_i2s_slv_apb4),
    .pslverr_uart_slv_apb4_tpv_i  (pslverr_uart_slv_apb4_tpv),
    .pslverr_spfs_slv_apb4_tpv_i  (pslverr_spfs_slv_apb4_tpv),
    .pslverr_i2s_slv_apb4_i  (pslverr_i2s_slv_apb4),
    .prdata_uart_slv_apb4_tpv_i   (prdata_uart_slv_apb4_tpv),
    .prdata_spfs_slv_apb4_tpv_i   (prdata_spfs_slv_apb4_tpv),
    .prdata_i2s_slv_apb4_i   (prdata_i2s_slv_apb4),
    .penable          (penable_apb),
    .pwrite           (pwrite_apb),
    .paddr            (paddr_apb),
    .pwdata           (pwdata_apb),
    .pprot            (pprot_apb),
    .pstrb            (pstrb_apb)

  );


  assign penable_uart_slv_apb4_tpv = penable_apb;
  assign penable_spfs_slv_apb4_tpv = penable_apb;
  assign penable_i2s_slv_apb4 = penable_apb;

  assign pwrite_uart_slv_apb4_tpv = pwrite_apb;
  assign pwrite_spfs_slv_apb4_tpv = pwrite_apb;
  assign pwrite_i2s_slv_apb4 = pwrite_apb;

  assign paddr_uart_slv_apb4_tpv = paddr_apb;
  assign paddr_spfs_slv_apb4_tpv = paddr_apb;
  assign paddr_i2s_slv_apb4 = paddr_apb;

  assign pwdata_uart_slv_apb4_tpv = pwdata_apb;
  assign pwdata_spfs_slv_apb4_tpv = pwdata_apb;
  assign pwdata_i2s_slv_apb4 = pwdata_apb;

  assign pprot_uart_slv_apb4_tpv = pprot_apb;
  assign pprot_spfs_slv_apb4_tpv = pprot_apb;
  assign pprot_i2s_slv_apb4 = pprot_apb;

  assign pstrb_uart_slv_apb4_tpv = pstrb_apb;
  assign pstrb_spfs_slv_apb4_tpv = pstrb_apb;
  assign pstrb_i2s_slv_apb4 = pstrb_apb;



  // ---------------------------------------------------------------------------
  // Instantiation of Timing Isolation Blocks
  // ---------------------------------------------------------------------------

  //  W Channel Timing Isolation Register Block on master_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 37
  nic400_amib_tpv_gp_apb4_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       37  // Payload Width
     )
  u_w_master_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn),
     .aclk                  (aclk),
     // inputs
     .src_valid             (w_master_port_src_valid),
     .src_data              (w_master_port_src_data),
     .dst_ready             (w_master_port_dst_ready),

     // outputs
     .src_ready             (w_master_port_src_ready),
     .dst_data              (w_master_port_dst_data),
     .dst_valid             (w_master_port_dst_valid)
     );



  // A channel is set to wires at master_port.

  // D channel is set to wires at master_port.

  // AW channel is set to wires at slave_port.

  // AR channel is set to wires at slave_port.

  // R channel is set to wires at slave_port.

  // W channel is set to wires at slave_port.

  // B channel is set to wires at slave_port.


//==============================================================================
// OVL Assertions
//==============================================================================
`ifdef ARM_ASSERT_ON

// Include Standard OVL Defines
`include "std_ovl_defines.h"

  //----------------------------------------------------------------------------
  // OVL_ASSERT: Lock Transaction received when not supported.
  //----------------------------------------------------------------------------
  //
  //----------------------------------------------------------------------------
  // OVL_ASSERT_RTL

  wire lock_rx_no_lock_support;

  // Signals that a locking transaction has been received when not supported.
  assign lock_rx_no_lock_support = 1'b0;


  assert_never #(`OVL_ERROR,
                 `OVL_ASSERT,
                 "AMIB: Lock transaction received when not supported.")
  amib_lock_no_lock_support
  (
    .clk        (aclk),
    .reset_n    (aresetn),
    .test_expr  (lock_rx_no_lock_support)
  );
  // OVL_ASSERT_END


  `endif // ARM_ASSERT_ON

endmodule

`include "nic400_amib_tpv_gp_apb4_undefs_ysyx_rv32.v"

// --================================= End ===================================--
